1. Field of the Invention
This invention relates to the field of integrated circuit memories. More particularly, this invention relates to power supply mechanisms used within such integrated circuit memories.
2. Description of the Prior Art
It is known to provide integrated circuit memories comprising an array of memory cells and power supply circuitry connected to the array to provide a voltage source to the memory cells within the array. Typically, each memory cell will be supplied with electrical power via a power rail at Vdd and a power rail at ground. In some memories it is known to alter the voltage difference between the different power supply rails in order, for example, to save electrical power.
It is also known within the field of integrated circuit memories to use increasingly small device geometries for forming the different components of the memory. For example, it is now becoming common to use process geometries of a 45 nm size. While the use of such small geometries improves the component density and generally reduces power consumption and cost, it has the disadvantage of being more susceptible to process variation whereby variations in the characteristics of individual devices away from their ideal design characteristics causes them to no longer operate as intended. The increased likelihood of such malfunctioning devices arising within an integrated circuit memory tends to reduce the manufacturing yield of correctly operating memories and accordingly increase the cost of such correctly operating memories.
It is desirable to provide integrated circuit memories which are more robust against manufacturing variation.